fpga或门代码，FPGA简单门电路怎么实现

很多朋友对fpga或门代码，FPGA简单门电路怎么实现不是很了解，每日小编刚好整理了这方面的知识，今天就来带大家一探究竟。

1.verilog实现基本门电路verilog实现反相器，2输入与门，2输入与非门，2输入或非门，2输入异或门，2输入异或门，2输入异或门；写一个仿真程序来测试实现；合成并实现模拟的verilog代码，下载到basys3进行验证。2.verilog实现2取2 1MUX编写仿真程序并测试；合成并实现模拟的verilog代码，下载到basys3进行验证。2.

Led [0] SW [0] SW [1]实现2输入与门LED [2] SW [2] SW [3]实现2输入或门LED [4] SW [4] SW [5]实现2输入与非门LED [6] SW [6] SW [7]实现2输入或非门LED [8] SW [7] 2。输入异或门LED [12] SW [12]实现反相器LED [13] SW [13] SW [14] SW [15]实现2取2 mux 3。实现模块FPGA 001(输入[15: 0] SW，输出[13:0]LED)；

Assign led [0]=SW [0] SW [1]; Assign LED [2]=SW [2] | SW [3]; Assign led [4]=~ (SW [4] SW [5]); Assign LED [6]=~ (SW [6] | SW [7]); Assignment led [8]=(SW [8] (~ SW [9]) | (~ SW [8] SW [9]); Assignment led [10]=~ ((SW [10] (~ SW [11]) | (~ SW [10] SW [11])); Assign LED [12]=~ SW [12]; Assign LED [13]=~ SW [13] SW [14] | SW [13] SW [15]; End module 4. test module

模块FD；reg[15:0]w；电线[13:0]l；fpga001 f(宽，长);initialbeginw=16 ' B0 # 10w=16 ' b 00100101010101；# 10w=16 ' b 0101101010101010101010；# 10w=16 ' b 0110010101010101# 10w=16 ' b 1001101010101010 # 10w=16 ' b 10100101010101；# 10w=16 ' b 1111101010101010101010；# 20 $ finishenditalbegin $ monitor($ time，"LED=%b"，w)；末端模块5 .引脚分布图##此文件是一个常规文件100 . basys 3版本B板的xdc # #在项目中使用：

## -取消对所用引脚对应的行的注释## -根据项目中的顶级信号名称重命名所用端口（每行中，获取端口之后)##时钟信号# set _ property PACKAGE _ PIN W5[get _ ports clk]# set _ property io标准LV CMOS 33[get _ ports clk]# create _ Clock-add-name sys _ clk _ PIN-period 10.00-waveform { 0 }[get _ ports clk]# # switch set _ property PACKAGE _ PIN V17[get _ ports { SW

set _ property io标准LV CMOS 33[get _ ports { SW[0]}]set _ property PACKAGE _ PIN V16[get _ ports { SW[1]}]set _ property io标准LV CMOS 33[get _ ports { SW[1]}]set _ property PACKAGE _ PIN W16[get _ ports { SW[2]}]set _ property io标准LV CMOS 33[get _ ports { SW[2]}]set _ property PACKAGE _ PIN W17[get _ ports { SW[3]}]set _ property

set _ property io标准LV CMOS 33[get _ ports { SW[4]}]set _ property PACKAGE _ PIN V15[get _ ports { SW[5]}]set _ property io标准LV CMOS 33[get _ ports { SW[5]}]set _ property PACKAGE _ PIN W14[get _ ports { SW[6]}]set _ property io标准LV CMOS 33[get _ ports { SW[6]}]set _ property PACKAGE _ PIN W13[get _ ports { SW[7]}]set _ property

set _ property io标准LV CMOS 33[get _ ports { SW[8]}]set _ property PACKAGE _ PIN T3[get _ ports { SW[9]}]set _ property io标准LV CMOS 33[get _ ports { SW[9]}]set _ property PACKAGE _ PIN T2[get _ ports { SW[10]}]set _ property io标准LV CMOS 33[get _ ports { SW[10]}]set _ property PACKAGE _ PIN R3[get _ ports { SW[11]}]set _ property io标准

set _ property io标准LV CMOS 33[get _ ports { SW[12]}]set _ property PACKAGE _ PIN U1[get _ ports { SW[13]}]set _ property io标准LV CMOS 33[get _ ports { SW[13]}]set _ property PACKAGE _ PIN T1[get _ ports { SW[14]}]set _ property io标准LV CMOS 33[get _ ports { SW[14]}]set _ property PACKAGE _ PIN R2[get _ ports { SW[15]}]set _ property

set _ property io标准LV CMOS 33[get _ ports { led[0]}]set _ property PACKAGE _ PIN E19[get _ ports { led[1]}]set _ property io标准LV CMOS 33[get _ ports { led[1]}]set _ property PACKAGE _ PIN U19[get _ ports { led[2]}]set _ property io标准LV CMOS 33[get _ ports { led[2]}]set _ property PACKAGE _ PIN V19[get _ ports { led[3]}]set _ property io支架

set _ property io标准LV CMOS 33[get _ ports { led[4]}]set _ property PACKAGE _ PIN U15[get _ ports { led[5]}]set _ property io标准LV CMOS 33[get _ ports { led[5]}]set _ property PACKAGE _ PIN U14[get _ ports { led[6]}]set _ property io标准LV CMOS 33[get _ ports { led[6]}]set _ property PACKAGE _ PIN V14[get _ ports { led[7]}]set _ property io支架

set _ property io标准LV CMOS 33[get _ ports { led[8]}]set _ property PACKAGE _ PIN V3[get _ ports { led[9]}]set _ property io标准LV CMOS 33[get _ ports { led[9]}]set _ property PACKAGE _ PIN W3[get _ ports { led[10]}]set _ property io标准LV CMOS 33[get _ ports { led[10]}]set _ property PACKAGE _ PIN U3[get _ ports { led[11]}]set _ property io

set _ property io标准LV CMOS 33[get _ ports { led[12]}]set _ property PACKAGE _ PIN N3[get _ ports { led[13]}]set _ property io标准LV CMOS 33[get _ ports { led[13]}]set _ property PACKAGE _ PIN P1[get _ ports { led[14]}]set _ property io标准LV CMOS 33[get _ ports { led[14]}]set _ property PACKAGE _ PIN L1[get _ ports { led[15]}]set _ property

# set _ property PACKAGE _ PIN W7[get _ ports { seg[0]}]# set _ property io标准LV CMOS 33[get _ ports { seg[0]}]# set _ property PACKAGE _ PIN W6[get _ ports { seg[1]}]# set _ property io标准LV CMOS 33[get _ ports { seg[1]}]# set _ property PACKAGE _ PIN U8[get _ ports { seg[2]}]# set _ property io标准LV CMOS 33[get _ ports { seg

# set _ property PACKAGE _ PIN U5[get _ ports { seg[4]}]# set _ property io标准LV CMOS 33[get _ ports { seg[4]}]# set _ property PACKAGE _ PIN V5[get _ ports { seg[5]}]# set _ property io标准LV CMOS 33[get _ ports { seg[5]}]# set _ property PACKAGE _ PIN U7[get _ ports { seg[6]}]# set _ property io标准LV CMOS 33[get _ ports { seg

# set _ property PACKAGE _ PIN U2[get _ ports { an[0]}]# set _ property io标准LV CMOS 33[get _ ports { an[0]}]# set _ property PACKAGE _ PIN U4[get _ ports { an[1]}]# set _ property io标准LV CMOS 33[get _ ports { an[1]}]# set _ property PACKAGE _ PIN V4[get _ ports { an[2]}]# set _ property io标准LV CMOS 33[get _ ports { an[2]}]]]#

# set _ property PACKAGE _ PIN U18[get _ ports btnC]# set _ property io标准LV CMOS 33[get _ ports btnC]# set _ property PACKAGE _ PIN T18[get _ ports btnU]# set _ property io标准LV CMOS 33[get _ ports btnU]# set _ property PACKAGE _ PIN W19[get _ ports btnL]# set _ property io标准LV CMOS 33[get _ ports btnL]# set _ property PACKAGE _ PIN T17[get _ ports btnR]# set _ property io标准

# set _ property io standard LV CMOS 33[get _ ports btnD]# # Pmod Header JA # # Sch name=JA1 # set _ property PACKAGE _ PIN J1[get _ ports { JA[0]}]# set _ property io standard LV CMOS 33[get _ ports { JA[0]}]# # Sch name=JA2 # set _ property PACKAGE _ PIN L2[get _ ports { JA[1]}]# set _ property io standard LV CMOS 33[get _ ports { JA[1]}]# # Sch

#set_property PACKAGE_PIN G2 get_ports {JA3}

#set_property IOSTANDARD LVCMOS33 get_ports {JA3}

##Sch name=JA7

#set_property PACKAGE_PIN H1 get_ports {JA4}

#set_property IOSTANDARD LVCMOS33 get_ports {JA4}

##Sch name=JA8

#set_property PACKAGE_PIN K2 get_ports {JA5}

#set_property IOSTANDARD LVCMOS33 get_ports {JA5}

##Sch name=JA9

#set_property PACKAGE_PIN H2 get_ports {JA6}

#set_property IOSTANDARD LVCMOS33 get_ports {JA6}

##Sch name=JA10

#set_property PACKAGE_PIN G3 get_ports {JA7}

#set_property IOSTANDARD LVCMOS33 get_ports {JA7}

##Pmod Header JB

##Sch name=JB1

#set_property PACKAGE_PIN A14 get_ports {JB0}

#set_property IOSTANDARD LVCMOS33 get_ports {JB0}

##Sch name=JB2

#set_property PACKAGE_PIN A16 get_ports {JB1}

#set_property IOSTANDARD LVCMOS33 get_ports {JB1}

##Sch name=JB3

#set_property PACKAGE_PIN B15 get_ports {JB2}

#set_property IOSTANDARD LVCMOS33 get_ports {JB2}

##Sch name=JB4

#set_property PACKAGE_PIN B16 get_ports {JB3}

#set_property IOSTANDARD LVCMOS33 get_ports {JB3}

##Sch name=JB7

#set_property PACKAGE_PIN A15 get_ports {JB4}

#set_property IOSTANDARD LVCMOS33 get_ports {JB4}

##Sch name=JB8

#set_property PACKAGE_PIN A17 get_ports {JB5}

#set_property IOSTANDARD LVCMOS33 get_ports {JB5}

##Sch name=JB9

#set_property PACKAGE_PIN C15 get_ports {JB6}

#set_property IOSTANDARD LVCMOS33 get_ports {JB6}

##Sch name=JB10

#set_property PACKAGE_PIN C16 get_ports {JB7}

#set_property IOSTANDARD LVCMOS33 get_ports {JB7}

##Pmod Header JC

##Sch name=JC1

#set_property PACKAGE_PIN K17 get_ports {JC0}

#set_property IOSTANDARD LVCMOS33 get_ports {JC0}

##Sch name=JC2

#set_property PACKAGE_PIN M18 get_ports {JC1}

#set_property IOSTANDARD LVCMOS33 get_ports {JC1}

##Sch name=JC3

#set_property PACKAGE_PIN N17 get_ports {JC2}

#set_property IOSTANDARD LVCMOS33 get_ports {JC2}

##Sch name=JC4

#set_property PACKAGE_PIN P18 get_ports {JC3}

#set_property IOSTANDARD LVCMOS33 get_ports {JC3}

##Sch name=JC7

#set_property PACKAGE_PIN L17 get_ports {JC4}

#set_property IOSTANDARD LVCMOS33 get_ports {JC4}

##Sch name=JC8

#set_property PACKAGE_PIN M19 get_ports {JC5}

#set_property IOSTANDARD LVCMOS33 get_ports {JC5}

##Sch name=JC9

#set_property PACKAGE_PIN P17 get_ports {JC6}

#set_property IOSTANDARD LVCMOS33 get_ports {JC6}

##Sch name=JC10

#set_property PACKAGE_PIN R18 get_ports {JC7}

#set_property IOSTANDARD LVCMOS33 get_ports {JC7}

##Pmod Header JXADC

##Sch name=XA1_P

#set_property PACKAGE_PIN J3 get_ports {JXADC0}

#set_property IOSTANDARD LVCMOS33 get_ports {JXADC0}

##Sch name=XA2_P

#set_property PACKAGE_PIN L3 get_ports {JXADC1}

#set_property IOSTANDARD LVCMOS33 get_ports {JXADC1}

##Sch name=XA3_P

#set_property PACKAGE_PIN M2 get_ports {JXADC2}

#set_property IOSTANDARD LVCMOS33 get_ports {JXADC2}

##Sch name=XA4_P

#set_property PACKAGE_PIN N2 get_ports {JXADC3}

#set_property IOSTANDARD LVCMOS33 get_ports {JXADC3}

##Sch name=XA1_N

#set_property PACKAGE_PIN K3 get_ports {JXADC4}

#set_property IOSTANDARD LVCMOS33 get_ports {JXADC4}

##Sch name=XA2_N

#set_property PACKAGE_PIN M3 get_ports {JXADC5}

#set_property IOSTANDARD LVCMOS33 get_ports {JXADC5}

##Sch name=XA3_N

#set_property PACKAGE_PIN M1 get_ports {JXADC6}

#set_property IOSTANDARD LVCMOS33 get_ports {JXADC6}

##Sch name=XA4_N

#set_property PACKAGE_PIN N1 get_ports {JXADC7}

#set_property IOSTANDARD LVCMOS33 get_ports {JXADC7}

##VGA Connector

#set_property PACKAGE_PIN G19 get_ports {vgaRed0}

#set_property IOSTANDARD LVCMOS33 get_ports {vgaRed0}

#set_property PACKAGE_PIN H19 get_ports {vgaRed1}

#set_property IOSTANDARD LVCMOS33 get_ports {vgaRed1}

#set_property PACKAGE_PIN J19 get_ports {vgaRed2}

#set_property IOSTANDARD LVCMOS33 get_ports {vgaRed2}

#set_property PACKAGE_PIN N19 get_ports {vgaRed3}

#set_property IOSTANDARD LVCMOS33 get_ports {vgaRed3}

#set_property PACKAGE_PIN N18 get_ports {vgaBlue0}

#set_property IOSTANDARD LVCMOS33 get_ports {vgaBlue0}

#set_property PACKAGE_PIN L18 get_ports {vgaBlue1}

#set_property IOSTANDARD LVCMOS33 get_ports {vgaBlue1}

#set_property PACKAGE_PIN K18 get_ports {vgaBlue2}

#set_property IOSTANDARD LVCMOS33 get_ports {vgaBlue2}

#set_property PACKAGE_PIN J18 get_ports {vgaBlue3}

#set_property IOSTANDARD LVCMOS33 get_ports {vgaBlue3}

#set_property PACKAGE_PIN J17 get_ports {vgaGreen0}

#set_property IOSTANDARD LVCMOS33 get_ports {vgaGreen0}

#set_property PACKAGE_PIN H17 get_ports {vgaGreen1}

#set_property IOSTANDARD LVCMOS33 get_ports {vgaGreen1}

#set_property PACKAGE_PIN G17 get_ports {vgaGreen2}

#set_property IOSTANDARD LVCMOS33 get_ports {vgaGreen2}

#set_property PACKAGE_PIN D17 get_ports {vgaGreen3}

#set_property IOSTANDARD LVCMOS33 get_ports {vgaGreen3}

#set_property PACKAGE_PIN P19 get_ports Hsync

#set_property IOSTANDARD LVCMOS33 get_ports Hsync

#set_property PACKAGE_PIN R19 get_ports Vsync

#set_property IOSTANDARD LVCMOS33 get_ports Vsync

##USB-RS232 Interface

#set_property PACKAGE_PIN B18 get_ports RsRx

#set_property IOSTANDARD LVCMOS33 get_ports RsRx

#set_property PACKAGE_PIN A18 get_ports RsTx

#set_property IOSTANDARD LVCMOS33 get_ports RsTx

##USB HID （PS/2）

#set_property PACKAGE_PIN C17 get_ports PS2Clk

#set_property IOSTANDARD LVCMOS33 get_ports PS2Clk

#set_property PULLUP true get_ports PS2Clk

#set_property PACKAGE_PIN B17 get_ports PS2Data

#set_property IOSTANDARD LVCMOS33 get_ports PS2Data

#set_property PULLUP true get_ports PS2Data

##Quad SPI Flash

##Note that CCLK_0 cannot be placed in 7 series devices. You can access it using the

##STARTUPE2 primitive.

#set_property PACKAGE_PIN D18 get_ports {QspiDB0}

#set_property IOSTANDARD LVCMOS33 get_ports {QspiDB0}

#set_property PACKAGE_PIN D19 get_ports {QspiDB1}

#set_property IOSTANDARD LVCMOS33 get_ports {QspiDB1}

#set_property PACKAGE_PIN G18 get_ports {QspiDB2}

#set_property IOSTANDARD LVCMOS33 get_ports {QspiDB2}

#set_property PACKAGE_PIN F18 get_ports {QspiDB3}

#set_property IOSTANDARD LVCMOS33 get_ports {QspiDB3}

#set_property PACKAGE_PIN K19 get_ports QspiCSn

#set_property IOSTANDARD LVCMOS33 get_ports QspiCSn

以上知识分享希望能够帮助到大家！